This workshop provides participants the necessary skills to create high-level-synthesis IPs using the Vitis HLS tool flow targeting PYNQ-Z2 and PYNQ-ZU board. Various techniques and directives which can be used in Vitis HLS to improve design performance and the essential steps to create a subsystem with the Arm® processor using the Vivado® IP integrator are introduced in detail.
The original labs have been developed to demonstarte the basic design flow on Vitis HLS. A PC running Microsoft Windows 10 professional edition is also able to run the labs. Linux machine to run the Vitis HLS tool is more recommended.
The project-based learning labs offer a straightforward, transparent, and intuitive approach to learning, with practical applications within the PYNQ framework. This includes the HLS kernel design methodology and the utilization of the Vitis Accelerated Library.
2024 : Add the new Project-based Learning Section, upgrade the tool version to 2023.2, adding support for KV260 Board, Jupyter Notebooks and tutorial sources for PYNQ-Z2 and KV260 under PYNQ framework has finished initial release
2022 : Upgrade the basic labs to Vitis HLS 2021.2, adding support for Boolean board. At this time, tutorial sources and docs for PYNQ-Z2 and PYNQ-ZU has finished initial release.
| Board File | Part Number | Hardware Bring Up | |
|---|---|---|---|
| PYNQ-Z2 | Download | xc7z020clg400-1 | Guide |
| PYNQ-ZU | Download | xczu5eg-sfvc784-1-e | Guide |
| KV260 | Pre-installed | xck26-sfvc784-2LV-c | Guide |
All the source files are located in the path of {this_repo}/sources
For Windows machine, deep path should also be avoided since the maximum supporting length of path for Windows is 260 characters.
| Project | Difficulty | Implementation | Key Concept | Interface | Board |
|---|---|---|---|---|---|
| FIR | Easy | Hand-written | Transferring Sequential Loops to Parallel Loops | Memory | PYNQ-Z2/KV260 |
| Sobel | Easy | Hand-written/ Vitis Vision Library |
Flexible Adoption of Vitis Vision Library Level 1 Kernels | Memory/ Stream |
PYNQ-Z2/KV260 |
| Convolution Filter | Easy | Hand-written | Best Practices for Data-driven Task-level Parallelism | Stream | PYNQ-Z2/KV260 |
| Matmult | Easy | Hand-written | Mapping the 2D Array to Customizable Memory | Memory | PYNQ-Z2/KV260 |
This lab provides a basic introduction to high-level synthesis using the Vitis HLS tool flow targeting PYNQ-Z2. You will use Vitis HLS in GUI mode to create a project. You will simulate, synthesize, and implement the provided design.
This lab introduces various techniques and directives which can be used in Vitis HLS to improve design performance. The design under consideration accepts an image in a (custom) RGB format, converts it to the Y’UV color space, applies a filter to the Y’UV image and converts it back to RGB.
This lab introduces various techniques and directives which can be used in Vitis HLS to improve design performance as well as area and resource utilization. The design under consideration performs Discrete Cosine Transformation (DCT) on an 8x8 block of data.
This lab illustrates the HLS design flow for generating IP from the Vitis™ HLS tool. The generated IP is then used to create a subsystem with the Arm® processor from a Zynq® UltraScale+™ MPSoC using the Vivado® IP integrator. The hardware from the Vivado Design Suite is imported into the Vitis environment, and the FIR application is then run on the PYNQ-ZU development board.
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